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HD66523
(240-Channel Common Driver with Internal LCD Timing Circuit)
Preliminary
Description
The HD66523 is a common driver for liquid crystal dot-matrix graphic display system. This device incorporates a 240 liquid crystal driver and an oscillator, and generates timing signals (line scanning signals and frame synchronizing signals) required for the liquid crystal display. It features a new LCD driving technique for better quality of display and low power dissipation. Combined with the HD66522, a 160-channel column driver with an internal RAM, the HD66523 is optimal for use in displays for portable information tools.
Features
* * * * * * * * * * LCD timing generator: 1/200, 1/240 duty cycle timing are generated internally. Number of LCD drivers: 240 Power supply voltage: 2.4V to 3.6V High voltage LCD drive circuit: 20V LCD driving technique: Multi-line addressing for low power consumption. Programmable vertical retrace period: zero to 192 lines Low power consumption Internal display off function On-chip oscillator combined with external resistor and capacitor. Package: TCP
1102
HD66523
Pin Description
Classification Power supply Symbol VCC GND VLCD1, VLCD2 VEE1, VEE2 VRH1, VRH2 VM1, VM2 Control signals VRL1, VRL2 M/6 DUTY Pin Name VCC GND VLCD VEE VRH VM VRL Master/ Slave Duty I/O Power supply Power supply Power supply Power supply -- -- -- I I Number of pins Functions 2 VCC-GND: logic power supply 2 2 2 2 2 2 1 1 LCD drive level power supply Power supply for LCD driving circuit
Select master or slave mode. Selects the display duty cycle. Low level: 1/200 display duty ratio High level: 1/240 display duty ratio Set vertical retrace period Control the display-off function. Turn off the LCD. During display off, all LCD driver output VM level Pin SHL switches the shift direction of the scanning direction. Reset the LSI internally. Oscillator with external resistor and capacitor Test pins, must be connected to GND. The bidirectional shift register shifts data at the falling edge of CL1. During master mode, this pin outputs a data transfer clock with a two times larger cycle than the internal oscillator (or the cycle of the external clock) with a duty of 50%. During slave mode, this pin inputs the external data transfer clock. During master mode, pin FLM outputs the first line marker signal. During slave mode, this pin inputs the external data first line marker signal. Output scanning function signals during master mode. Input scanning function signals during slave mode. This pin shows vertical retrace period. Select one from among three levels, VRH, VM and VRL.
BP4 to BP0
'2& ',632))
SHL
Blanking period Display off control Display off
I I/O I
5 1 1
Shift left Reset Oscillator
I I -- I I/O
1 1 3 2 1
5(6(7
CR, C, R
LCD timing
TEST1, TEST0 Test CL1 Clock 1
FLM
First line marker
I/O
1
FX1, FX0
Scanning function Blank X1 to X240
I/O
2
BLANK LCD drive X1 to X240 output
O O
1 240
1103
HD66523
Table 1
M/$ $ H L
M/$ Signal Status $
Mode Master Slave LCD Timing Generator 1/200 or 1/240 duty cycle Stops Status of CL1, FLM and Output Input
Table 2
BP4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Retrace period
BP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Horizontal Retrace Period Number of lines 0 6 12 18 24 30 36 42 48 54 60 66 72 78 84 90 96 102 108 114 120 126 132 138 145 150 156 162 168 174 180 186
1104
HD66523
Table 3
SHL H L
Shift Direction
DUTY H L H L Shift Direction X240 X1 X200 X1 X1 X240 X1 X200
1105
HD66523
Internal Block Diagram
X1 to X240
VRH1 VM1 VRL1 VRH2 VM2 VRL2
LCD driver
240
Decoder
VRH-VRL VCC-GND 240
Level shifter
240
Level shifter
Selector
LCD timing generator
Scanning function generator
I/O control Oscillator
CR R
C
RESET BLANK CL1
FLM DOC DISPOFF FX0 FX1 TEST1 TEST0 M/S DUTY BP4~0 SHL
1. CR Oscillator: The CR oscillator generates the HD66523 operation clock. During master mode, since the operation clock is needed, connect oscillation resistor Rf with oscillation capacitor Cf. When the external clock is used. Input external clock to pin CR and open pins C and R (Figure 1). When using the HD66523 during slave mode, the operation clock will not be needed; therefore, connect pin CR to VCC and open pins C and R (Figure 2). 2. Liquid Crystal Timing Generator: The liquid crystal timing generator creates various signals for the LCD. During master mode (M/6 = VCC), the generator operates the HD66523's internal circuitry as a common internal driver using the generated LCD signals. In addition, signals CL1, FLM and '2& created by this generator can synchronously display data on a liquid crystal display by inputting them into the RAM-provided segment driver HD66522 used together with HD66523. During slave mode (M/6 = GND), this generator stops; the slave HD66523 operates based on signals CL1, '2& and FLM generated by the master HD66523.
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HD66523
C R CR C R Rf OPEN OPEN External clock Cf CR
Figure 1 Oscillator Connection in Master Mode
C
R
CR
OPEN OPEN
VCC
Figure 2 Oscillator Connection in Slave Mode 3. Scanning Function Generator: During master mode, this circuit generates the scanning function signals. During slave mode, this circuit stops working and FX1 and FX0 must be supplied from master HD66523. 4. Selector: The selector generates signals which select two lines of LCD driver. 5. Decoder: Outputs data according to scanning function signals and data. 6. LCD driver: Outputs one of three levels according to outputs from decoder.
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HD66523
Internal Function Description 1. Generation of Signals CL1 and FLM: Signal CL1 shifts the scanning signal of the common driver. It is a 50% duty-ratio clock that changes level synchronously with the rising edge of oscillator clock CR. FLM is a clock signal that goes high once every frame. One frame consists of display lines, 240 lines if DUTY is high and 200 lines if DUTY is low, and vertical retrace period which is set with BP4 to BP0. 2. Auto Display-off Control: This functions prevents incorrect display after reset release. The display is turned off four frames following after reset release. In addition, the display off control signal shown in Figure 4 is output by pin '2&. This pin is connected to pin ',632)) of the HD66522.
Vertical retrace period CR CL1 FLM
240 (200) 1 2
Figure 3 Generation of Signals CL1 and FLM
RESET FLM DOC
1 2 3 4 5
Figure 4 Automatic Display-off Control Function
1108
HD66523
Application Examples
Outline of HD66523 System Configuration The HD66523 system configuration is outlined in Figure 5 and 6. Refer to the connection list (Table 4) for connection details. * When a signal HD66523 is used to configure a small display (Figure 5) * When two HD66523s are used to configure a large display (Figure 6)
To HD66522 LCD When using the internal oscillator When using an external oscillator
No.1 Refer to connection list A Refer to connection list D
No.1
COM1 to COM240
Note: One HD66523 drives common signals and supplies timing signal to the HD66522.
Figure 5 System Configuration When Using a Single HD66523
To HD66522 LCD COM1 No.1 to COM240 COM241 to No.2 COM480 To HD66522 Note: Upper and lower displays are driven by separate HD66523s to ensure display quality. No.1 operates in master mode, and No.2 operates in slave mode. Lower display Upper display No.1 When using the internal oscillator When using an external oscillator Refer to connection list B Refer to connection list E No.2 Refer to connection list C Refer to connection list C
Figure 6 System Configuration When Using a Two HD66523
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1110
DISPOFF CR From Rf controller C f CL1 To CL1 of HD66522 Rf From controller C f Cf H -- -- From CL1 From FLM From DOC of HD66523 of HD66523 of HD66523 To CL1 of HD66522 To FLM of HD66522 Rf R Rf C Cf FLM To FLM of HD66522 FX1 and FX0 DOC SHL X1 to X240 COM1 to COM240 To DISPOFF To FX1 and FX0 H of HD66522 of HD66522 L COM240 to COM1 COM1 to COM240 COM240 to COM1 COM241 to COM480 COM480 to COM241 COM1 to COM240 COM240 to COM1 COM1 to COM240 COM240 to COM1 To DISPOFF To FX1 and FX0 H of HD66522 of HD66522, L HD66523 To DOC of HD66523 To FLM of HD66522, HD66523 To DISPOFF To FX1 and FX0 H of HD66522 of HD66522, L HD66523 To DOC of HD66523 To FX1 and FX0 H of HD66523 L RESET From MPU or external reset circuit From MPU or external reset circuit To CL1 of HD66522, HD66523 To FLM of HD66522, HD66523 From MPU H or external reset circuit From MPU From External or external controller Clock reset circuit -- -- From MPU From External or external controller Clock reset circuit -- -- To CL1 of HD66522, HD66523 Sets the number of lines for retrace period Sets the number of lines for retrace period Sets the number of lines for retrace period To DISPOFF To FX1 and FX0 H of HD66522 of HD66522 L
HD66523
Table 4 HD66523 Connection List
Connection M/S DUTY BP4 to BP0 Example Sets the number H H A of lines for retrace period B H H Sets the number of lines for retrace period
C
L
H
D
H
H
E
H
H
Notes: H = VCC (Fixed) L = GND (Fixed) "--" means "open" Rf: Oscillation resistor Cf: Oscillarion capacitor
HD66523
Example of System Configuration (1)
Figure 7 shows system configuration for a 240 * 160 dots LCD panel using segment driver HD66522 with internal bit-mapped RAM. All required functions can be prepared for liquid crystal display with just two LSIs except for liquid crystal display power supply circuit functions. 240
LS0 LS1 LS2 SHL
SEG1 SEG2
HD66522 (ID No.0)
LCD
SEG159 SEG160 COM1 COM2
Scanning direction
X1 to X240
FLM,CL1, FX1, FX0 DOC
DOC DISPOFF CR
LCD drivers
4 1
COM239 COM240
160
HD66523
LCD timing generator
R C
DUTY SHL M/S
BP4 to BP0 5 RESET
1 VCC
VCH, VM, VCL, VLCD, VEE
VRH, VM, VRL, VLCD, VEE 1 DISPOFF
17 8 3
A0 ~ A16 DB0 ~ DB7 CS,WE,OE
Power supply circuit
Figure 7 System Configuration (1)
1111
HD66523
Example of System Configuration (2)
Figure 8 shows a system configuration for a 240 * 320 dots LCD panel using segment driver HD66522 with internal bit-mapped RAM. 240
LS0 LS1 LS2 SHL
SEG1 SEG2
HD66522 (ID No.0)
LCD
SEG159 SEG160 SEG161 SEG162
HD66522 (ID No.2)
VCC
X1 to X240
4 1 FLM,CL1, FX1, FX0 DOC
DOC DISPOFF CR
LCD driver
COM239 COM240
SEG319 SEG320 COM1 COM2
Scanning direction
LS0 LS1 LS2 SHL
320
HD66523
LCD timing generator
R C
DUTY SHL M/S
BP4 to BP0 5 RESET
1 VCC
VCH, VM, VCL, VLCD, VEE VRH, VM, VRL, VLCD, VEE 1 17 8 3 A0 ~ A16 DB0 ~ DB7 CS,WE,OE DISPOFF
Power supply circuit
Figure 8 System Configuration (2)
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HD66523
Example of System Configuration (3)
Figure 9 shows a system configuration for a 320 * 480 dots LCD panel using segment driver HD66522 with internal bit-mapped RAM.
A0 ~ A16 DB0 ~ DB7 CS,WE,OE
17 8 3
VCC
RESET 1
1
DISPOFF1
FLM,CL1, FX1, FX0
3
BP4 to BP0
6
LS0 LS1 LS2 SHL
HD66522 (ID No.0) 320
HD66522 (ID No.2)
LS0 LS1 LS2 SHL
COM241 COM242
SEG159 SEG160
SEG161 SEG162
VCC VCC LS0 LS1 LS2 SHL
320 HD66522 (ID No.1) HD66522 (ID No.3)
LS0 LS1 LS2 SHL
SEG319 SEG320
COM479 COM480 SEG1 SEG2
VCC
Power supply circuit
VRH, VM, VRL, VLCD, VEE
VCH, VM, VCL, VLCD, VEE
Figure 9 System Configuration (3)
480
COM239 COM240
Scanning direction
DOC CR R C DUTY SHL M/S DOC CR
COM1 COM2
SEG2 SEG1
SEG160 SEG159
SEG162 SEG161
SEG320 SEG319
Master mode
RESET
X1 to X240
HD66523
DISPOFF
LCD driver
LCD
OPEN OPEN
X1 to X240
R C
DUTY SHL M/S
Slave mode
FLM,CL1, FX1, FX0
HD66523 BP4 to BP0
LCD driver
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HD66523
LCD Drive Output
HD66523 outputs one of three levels, VRH, VM and VRL. VM is unselected level, VRH is high select level and VRL is low select level. Either VRH or VRL level is selected depending on the number of flames and lines. Output timings are showed in Figure 10 to 12.
FLM CL1 FX1,FX0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10
VRH VM VRL 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 10 LCD Drive Output Timing at 3n + 1's frame (n = 1, 2, 3, )
FLM CL1 FX1,FX0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10
VRH VM VRL 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 11 LCD Drive Output Timing at 3n + 2's frame (n = 1, 2, 3, )
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HD66523
FLM CL1 FX1,FX0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12
VRH VM VRL 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 12 LCD Drive Output Timing at 3n + 3's frame (n = 1, 2, 3, )
1115
HD66523
Power Supply Circuit
The example of power circuit is shown in Figure 13. When you want to change contrast, both levels, VRH and VRL must be changed.
VLCD VRH (COM)
VLCD (variable) VDD (fixed) VCC -
+
VCC
VCH (SEG)
GND
DC/DC Converter
-
+
VM (COM, SEG)
-
+
VCL (SEG) GND
VEE (variable)
VEE VRL (COM)
Note: VM level must keep following equations;
(VRH-VM) = (VM-VRL) (VCH-VM) = (VM-VCL) VCL > GND VCH < VDD
Figure 13 Example of Power Supply Circuit
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HD66523
Absolute Maximum Ratings
Item Power voltage Logic circuit LCD drive circuit Symbol VCC VRH VRL Input voltage (1) Input voltage (2) Operating temperature Storage temperature VT1 VT2 Topr Tstg Rating -0.3 to + 7.0 -0.3 to +25.0 -20.0 to +0.3 -0.3 to VCC +0.3 VEE - 0.3 to VLCD + 0.3 -20 to + 75 -40 to + 125 Unit V V V V V C C 1, 2 1, 3 Note 1
Notes: 1. The reference point is GND (0V) 2. Applies to pins M/6, DUTY, BP4 to BP0, '2&, ',632)), SHL, 5(6(7, CR, CL1, FLM, FX0 to FX1, and TEST1 to TEST0. 3. Applies to pins VM1 and VM2. Supply the same voltage to pairs VRH1 and VRH2, VM1 and VM2, VRL1 and VRL2. 4. If the LSI is used beyond its absolute maximum rating, it may be permanently damaged. It should always be used within the limits of its electrical characteristics in order to prevent malfunction or unreliability.
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HD66523
Electrical Characteristics
DC Characteristics (VCC = 2.4 to 3.6V, GND = 0V, VLCD = 18 to 23V, VEE = -12 to -17V, Ta = -20 to +75C)
Item Input high level voltage Input low level voltage Output high level voltage Output low level voltage Input leakage current (1) Input leakage current (2) Vi-Vj ON resistance Applicable Symbol Pins VIH1 VIL1 VOH VOL IIL1 IIL2 RON min. typ. max. VCC 0.2 x VCC -- 0.1 x VCC 2.5 25 Unit V V V V A A IOH = -50 A IOL = 50 A VIN = VCC to GND Measurement Condition Note s 1 1 2 2 1
0.8 x VCC -- 0 --
0.9 x VCC -- -- -2.5 VRH1, VRH2, -25 VM1, VM2 VRL1, VRL2 X1 to X240 -- -- -- -- --
VIN = VLCD to VEE 1 ION = 100A 3
1.0 --
2.0 T.B.D.
k A
4 Master mode 1/240 duty cycle, Cf = 100pF Rf = 180k VCC = 3.0V Current ISL -- -- T.B.D. A Slave mode 4 consumption (2) 1/240 duty cycle, fCL = 16.8 kHz, VCC = 3.0V Current ILCD -- -- T.B.D. A Master mode 4 consumption (3) 1/240 duty cycle, Cf = 100pF Rf = 180k VCC = 3.0V VLCD = 23V VEE = -17V Notes: 1. Applied to input pins M/6, DUTY, BP4 to BP0, ',632)), SHL, 5(6(7, TEST1, TEST0 and CR, and I/O pins, '2&, CL1 and FLM during input state. 2. Applied to output pins, FX1 and FX0, and I/O pins, '2&, CL1 and FLM, during output stagte. 3 Indicates the resistance between on pin from X1 to X240 and another pin from the V pins, VRH1/VRH2, VM1/VM2 and VRL1/VRL2, when load current is applied to the X pin; defined under the following conditions: VRH = +23V, VRL = -17V VM = 1/2 * (VRH-VRL) 4. Input and Output currents are excluded. When a CMOS input is floating, excess current flows from the power supply to the input circuit. To avoid this, ViH and ViL must be held to VCC and GND levels, respectively. Current IMS consumption (1)
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HD66523
Item Operating frequency (1) Operating frequency (2) Oscillation frequency External clock duty External clock rising time External clock falling time Symbol fopr1 min. 10 typ. -- max. 200 Unit. kHz Measurement Condition Master mode (External clock operation) Slave mode frequency of CL1 Cf = 100pF Rf = 180k Master mode Master mode Master mode 3 3 3 Notes 1
fopr2 fOSC Duty tr tf
5 30 45 -- --
-- 36 50 -- --
100 42 55 100 100
kHz kHz % ns ns
2
Notes: 1. External clock is supplied to CR pin during master mode, and C and R pins must be left open. 2. Applies to the clock which is supplied to CL1 during slave mode. CR must be connected to GND, and C and R pins must be left open. 3. Applies to the external clock which is supplied to CR during a master mode.
tH
tL
0.8*VCC 0.5*VCC 0.2*VCC tr tf Duty =
tH tH + tL
x 100%
Figure 14 External Clock
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HD66523
AC Characteristic (VCC = 2.4 to 3.6V, GND = 0V, Ta = -20 to 75C)
No. (1) (2) (3) (4) (5) (6) (7) Item CL1 high-level width CL1 low-level width CL1 rise time CL1 fall time FLM setup time FLM hold time CL1 delay time Symbol tCWH tCWL tr tf tFS tFH tCL1 Applicable Pins min. CL1 CL1 CL1 CL1 FLM, CL1 FLM, CL1 CL1 FLM 1.0 1.0 -- -- 2.0 1.0 1.0 1.0 max. -- -- 100 100 -- -- -- -- Units s s ns ns s s s s Notes 1 1 1 1 1 1 2 2
(8) FLM delay time tDFLM Notes: 1. Applies during slave mode 2. Applies during master mode
tr (3) (1) t CWH
tf (4)
(2) t CWL
CL1
0.8VCC 0.2VCC (5) t FS 0.8VCC (6) t FH
FLM
Figure 15 Slave Mode Timing
0.8VCC CR (7) t DCL1 0.2VCC (7) t DCL1
0.8VCC CL1 0.2VCC (8) t DFLM (8) t DFLM
0.8VCC FLM 0.2VCC
Figure 16 Master Mode Timing
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